In producing integrated circuits for power applications it is typical to use a process utilizing a lateral double diffused MOS (LDMOS) technology. In designing a transistor cell for this technology, the size of the cell is limited in the prior art largely due to the need for a good source to backgate contact. In order to make this contact sufficiently efficient and of low impedance, the area of the cell must be large enough such that the figure of merit contact resistance is kept below a critical level. However, this cell size is a critical factor in producing smaller geometry circuits and improving the density of devices and efficient layout schemes. Therefore it is desirable to provide a transistor cell for a process using a lateral DMOS technology having smaller feature sizes for lower power consumption and better performance.
Heretofore, in this field, ICs using LDMOS processes have featured vertically integrated power DMOS devices mainly centered around hexagonal layouts and later square shaped cell layouts. These particular cell geometries have been found to offer reasonably large amounts of channel width for a given cell area. The hexagonal shaped cells are usually found in the vertical cell technologies. Alternatively, topside drain contact arrangements or updrain DMOS devices have been evolving from the vertical devices and can be characterized for the most part as lateral or semi-lateral devices. Semi-lateral DMOS devices have evolved out of the vertical DMOS devices, with the use of buried N+ material under cell arrays and deeply diffused N+ sinker regions between array cells. Square cell arrays have become the most popular cells in recent use since they are easily modeled as elaborate equivalent resistor networks, easy to array and nicely laid out.
However, the prior art approaches to improving cell sizing and spacing are limited to sizes needed for efficient source and backgate contacts along with process technology tolerances. The cell spacing and cell size is limited as a function of the minimum polysilicon window widths needed to make the required source-backgate contact while maintaining proper design rule spacing from the gate contact. A need for a cell which will allow smaller spacing and cell size with improved performance thus exists.